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| PRELIMINARY CY7C1071AV33 32-Mbit (2M x 16) Static RAM Features * High density 32-Mbit SRAM * High speed -- tAA = 10 ns * Low active power -- ICC = 450 mA * Operating voltages of 3.3 0.3V * 2.0V data retention * Automatic power-down when deselected * TTL-compatible inputs and outputs * Available in standard 119-ball FBGA Low Enable (BLE) is LOW, then data from the I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A20). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A20). Reading from the device is accomplished by enabling the chip by taking CE HIGH while forcing the Output Enable (OE) LOW and the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of Read and Write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE LOW), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a Write operation (CE HIGH, and WE LOW). The CY7C1071AV33 is available in a 119-ball grid array (FBGA) package. Functional Description The CY7C1071AV33 is a 3.3V high-performance 32-Megabit static RAM organized as a 2,097,152 words by 16 bits. Writing to the device is accomplished by enabling the chip (CE HIGH) while forcing the Write Enable (WE) input LOW. If Byte Logic Block Diagram DATA-IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 2048K x 16 RAM Array SENSE AMPS I/O0-I/O7 I/O8-I/O15 COLUMN DECODER BHE WE CE OE BLE Power-down Circuit A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 CE Cypress Semiconductor Corporation Document #: 38-05634 Rev. *A * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised September 1, 2005 PRELIMINARY Selection Guide CY7C1071AV33-10 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Com'l / Ind'l Com'l / Ind'l 10 450 100 CY7C1071AV33 CY7C1071AV33-12 12 400 100 Unit ns mA mA Pin Configurations 119 BGA (Top View) 1 A B C D E F G H J K L M N P R T U NC NC NC NC I/O8 I/O9 I/O10 I/O11 NC I/O12 I/O13 I/O14 I/O15 NC NC NC NC 2 A A BHE VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD A A A 3 A A CE VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS NC A A 4 A NC A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A WE OE 5 A A NC VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS NC A A 6 A A BLE VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD A A A 7 NC NC NC NC I/O0 I/O1 I/O2 I/O3 DNU I/O4 I/O5 I/O6 I/O7 NC NC NC NC Document #: 38-05634 Rev. *A Page 2 of 10 PRELIMINARY Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND [1] CY7C1071AV33 Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA Operating Range Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 3.3V 0.3V .... -0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[1] ....................................-0.3V to VCC + 0.3V DC Input Voltage[1] .................................-0.3V to VCC + 0.3V DC Electrical Characteristics Over the Operating Range -10 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-down Current --TTL Inputs Automatic CE Power-down Current --CMOS Inputs GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX = 1/tRC Com'l / Ind'l CE <= VIL, Max. VCC,VIN > VIH or VIN < VIL, f = fMAX CE <= 0.3V, Max. VCC, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 Com'l / Ind'l Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.0 -0.3 -2 -2 Min. 2.4 0.4 VCC + 0.3 0.8 +2 +2 450 140 2.0 -0.3 -2 -2 Max. Min. 2.4 0.4 VCC + 0.3 0.8 +2 +2 400 140 -12 Max. Unit V V V V A A mA mA ISB2 100 100 mA Capacitance[2] Parameter CIN COUT I/O Capacitance Description Input Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 12 15 Unit pF pF Thermal Resistance[2] Parameter JA JC Description Thermal Resistance (Junction to Ambient)[2] Thermal Resistance (Junction to Case)[2] Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board All-Packages TBD TBD Unit C/W C/W Notes: 1. VIL (min.) = -2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns. 2. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05634 Rev. *A Page 3 of 10 PRELIMINARY AC Test Loads and Waveforms[3] 50 OUTPUT Z0 = 50 30 pF* VTH = 1.5V 3.3V OUTPUT 5 pF* INCLUDING JIG AND SCOPE (b) R1 317 CY7C1071AV33 R2 351 (a) * Capacitive Load consists of all components of the test environment. ALL INPUT PULSES 3.3V 90% GND Rise time > 1 V/ns 10% 90% 10% Fall time: > 1 V/ns [4] (c) AC Switching Characteristics Over the Operating Range Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write tWC tSCE Cycle[8, 9] Write Cycle Time CE HIGH to Write End VCC(typical) to the first access[5] Read Cycle Time Address to Data Valid Data Hold from Address Change CE HIGH to Data Valid OE LOW to Data Valid OE LOW to Low-Z OE HIGH to High-Z[6] CE HIGH to Low-Z[6] CE LOW to High-Z[6] CE HIGH to Power-Up[7] CE LOW to Power-Down[7] Byte Enable to Data Valid Byte Enable to Low-Z Byte Disable to High-Z Description -10 Min. 1 10 10 3 10 5 1 5 3 5 0 10 10 1 5 10 7 12 8 1 0 3 1 3 Max. Min. 1 12 -12 Max. Unit ms ns 12 12 6 6 6 12 12 6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1 ms (Tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and specified transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise. 5. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 6. tHZOE, tHZCE, tHZWE, tHZBE and tLZOE, tLZCE, t\LZWE, tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 7. These parameters are guaranteed by design and are not tested. 8. The internal Write time of the memory is defined by the overlap of CE HIGH and WE LOW. Chip enables must be active and WE and byte enables must be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05634 Rev. *A Page 4 of 10 PRELIMINARY AC Switching Characteristics Over the Operating Range (continued)[4] -10 Parameter tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Description Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE HIGH to Low-Z[6] WE LOW to High-Z [6] CY7C1071AV33 -12 Max. Min. 8 0 0 8 6 0 3 5 7 8 6 Max. Unit ns ns ns ns ns ns ns ns ns Min. 7 0 0 7 5.5 0 3 Byte Enable to End of Write Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR tCDR[2] tR [10] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Com'l / Ind'l Conditions[11] VCC = VDR = 2.0V, CE < 0.3V VIN > VCC - 0.3V or VIN < 0.3V Min. 2.0 Max 100 Unit V mA ns s 0 Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR CE VDR > 2V 3.0V tR Switching Waveforms Read Cycle No. 1[11, 13] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Notes: 10. Test conditions assume tf < 3 ns. 11. No input may exceed VCC + 0.3V. 12. Device is continuously selected. OE, BHE and/or BHE = VIL. CE = VIH. 13. WE is HIGH for Read cycle. Document #: 38-05634 Rev. *A Page 5 of 10 PRELIMINARY Switching Waveforms (continued) Read Cycle No. 2 (OE Controlled)[13, 14] CY7C1071AV33 ADDRESS tRC CE tACE OE BHE,BLE tDOE tLZOE tDBE tLZBE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZCE tHZBE DATA VALID tPD 50% ISB IICC CC tHZOE HIGH IMPEDANCE DATA OUT Write Cycle No. 1 (CE Controlled)[15, 16] tWC ADDRESS tSCE tSA CE tAW tPWE WE tBW BHE,BLE tSD DATA I/O tHD tHA Notes: 14. Address valid prior to or coincident with CE transition HIGH. 15. Data I/O is high-impedance if OE or BHE and/or BLE = VIH. 16. If CE goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05634 Rev. *A Page 6 of 10 PRELIMINARY Switching Waveforms (continued) Write Cycle No. 2 (BLE or BHE Controlled)[15, 16] tWC ADDRESS CY7C1071AV33 BHE,BLE tSA tBW tAW tPWE WE tSCE CE tSD DATA I/O tHD tHA Write Cycle No. 3 (WE Controlled, OE LOW)[15, 16] tWC ADDRESS tSCE CE tAW tSA tPWE tHA WE tBW BHE,BLE tHZWE DATA I/O tLZWE tSD tHD Document #: 38-05634 Rev. *A Page 7 of 10 PRELIMINARY Truth Table CE L H H H H H H H OE X L L L X X X H WE X H H H L L L H BLE X L L H L L H X BHE X L H L L H L X I/O0-I/O7 High-Z Data Out Data Out High-Z Data In Data In High-Z High-Z I/O8-I/O15 High-Z Data Out High-Z Data Out Data In High-Z Data In High-Z Power-down Read All Bits Read Lower Bits Only Read Upper Bits Only Write All Bits Write Lower Bits Only Write Upper Bits Only Mode CY7C1071AV33 Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Selected, Outputs Disabled Ordering Information Speed (ns) 10 12 Ordering Code CY7C1071AV33-10 BBC CY7C1071AV33-10 BBI CY7C1071AV33-12 BBC CY7C1071AV33-12 BBI BB119 119-Ball (14 x 22 x 2.02 mm) FBGA Package Name BB119 Package Type 119-Ball (14 x 22 x 2.02 mm) FBGA Operating Range Commercial Industrial Commercial Industrial Document #: 38-05634 Rev. *A Page 8 of 10 PRELIMINARY Package Diagram 119 FBGA (14 x 22 x 2.02 mm) BB119B CY7C1071AV33 51-85210-** All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05634 Rev. *A Page 9 of 10 (c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY Document History Page Document Title: CY7C1071AV33 32-Mbit (2M x 16) Static RAM Document Number: 38-05634 REV. ** *A Orig. of ECN NO. Issue Date Change 278072 397695 See ECN See ECN RKF SYT New Datasheet Description of Change CY7C1071AV33 Converted from "Advance Information" to "Preliminary" Changed the MPN from CYM1071AV33 to CY7C1071AV33 Changed Title from "CY7C1071AV33 32-Mbit (2M x 16) Static RAM Module" to "CY7C1071AV33 32-Mbit (2M x 16) Static RAM " Changed address of Cypress Semiconductor Corporation on Page# 1 from "3901 North First Street" to "198 Champion Court" Removed redundant information from the "Features" and "Functional Description" sections Edited typo `A19' to `A20' in the Functional Description on Page # 1 Changed Package offering from 119 PBGA (BG119) to 119 FBGA (BB119) Removed the Package Column from the Capacitance table on Page # 3 Changed the DC Voltage Applied to Outputs in High-Z State and DC Input Voltage from "-0.5V to VCC + 0.5V" to "-0.3V to VCC + 0.3V" in the Maximum Ratings on Page # 3 Changed tDBE from 5 ns to 10 ns and 6 ns to 12 ns for -10 and -12 speed bins respectively on Page # 4 Included spec for ICCDR = 100 mA in the Data Retention Characteristics table on Page# 5 Edited footnote # 11 from "VCC + 0.5V" to "VCC + 0.3V" Referenced footnotes # 15 and 16 on to Write Cycle No.2 Page # 7 Updated the Ordering Information to include the BB119 Package Document #: 38-05634 Rev. *A Page 10 of 10 |
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